This invention relates in general to the field of semiconductor electronic devices, and more particularly to an improved microelectronic interconnect copper metallization structure having a cobalt-based or ruthenium-based adhesion promotion layer between diffusion barrier and copper layers and method of fabricating the same.
Microelectronic semiconductor integrated circuit chip fabrication technology has focused on techniques and materials to produce smaller and faster devices with increasing packing densities for higher performance chips. This trend towards miniaturization has led to demand for improved semiconductor integrated circuit (IC) interconnect performance and improved manufacturability, resulting in a shift from conventional Al/SiO2 interconnect architectures to copper-based metallization in conjunction with low-permitivity (or low-k) dielectrics. Compared to aluminum, Copper metallization reduces interconnect propagation delays, reduces cross-talk, and enables higher interconnect current densities with extended electro migration lifetime. When combined with low-k dielectrics, copper metallization can also decrease the number of metallization levels, resulting in reduced chip manufacturing costs. For instance, the superior electro migration performance and lower resistivity of copper compared to aluminum, permits a reduction in metal stack height that results in reduced signal cross-talk and improved interconnect speed.
A number of deposition methods, such as chemical-vapor deposition (CVD), physical-vapor deposition (PVD), and electrochemical deposition (ECD) or plating can be used for deposition of uniform thin-film copper layers. Chemical-vapor deposition, in particular, provides a number of advantages over other deposition techniques, including the capability for fully vacuum cluster integrated deposition of the diffusion barrier and copper layers through cluster tool equipment. Metal-organic CVD (MOCVD) is a particularly desirable means for deposition of copper due to its excellent gap-fill characteristics, such as is desirable for high-aspect ratio via holes and trenches, its excellent step coverage, its compatibility with single/dual damascene processing, and its relatively low thermal budget, such as less than 250xc2x0 C. deposition process temperature, which helps ensure compatibility with low-k polymer dielectrics. Due to these advantages, as device dimensions shrink, MOCVD technology is likely to replace other deposition techniques as the preferred solution for deposition of uniform high-conductivity copper layers.
Although copper provides a number of advantages for microelectronic semiconductor chip performance, significant difficulties exist in depositing and reliably integrating copper layers on a substrate. One difficulty relates to rapid diffusion of copper atoms through many materials, including both metals and dielectrics. Copper tends to diffuse through device materials during the thermal cycling that a semiconductor substrate experiences during the multi-level interconnect fabrication process flow, as well as during actual chip operation under applied electric fields. Copper diffusion into and/or through the inter-metal dielectric (IMD) results in current leakage between adjacent metal lines, known as line-to-line leakage. Copper diffusion through the IMD and pre-metal dielectric (PMD) or inter-level dielectric (ILD) and into the transistor regions results in degraded device characteristics such as accelerated aging and, potentially, non-functional transistor and chips.
Another difficulty associated with copper in microelectronic device fabrication, such as semiconductor IC fabrication, is the sufficient adhesion of the copper to the underlying barrier to prevent copper delamination during subsequent chemical-mechanical polishing (CMP). Moreover, copper is prone to corrosion and must be passivated. Non-conducting diffusion barriers, such as Si3N4, are ideal for passivation and prevention of copper diffusion between metallization layers. However, for many applications, a conducting barrier is necessary. For instance, a conducting barrier is necessary to enable electrical current flow between via plugs and lower level metal lines. To reduce copper diffusion and corrosion, a number of advanced diffusion barriers have been developed to supplant traditional barriers used with aluminum and tungsten metallization, such as TiN and TiW barriers. For instance, some barrier materials proposed for use with copper metallization include Ta, TaN, WNx, and ternary barrier materials such as TiSiN, TaSiN, WSiN, and WBN. Although these barriers improve reliability of copper metallization in microelectronic devices, these conventional barriers have some significant difficulties including poor adhesion with as deposited copper and sometimes with other adjacent layers, such as low-K dielectrics.
Other potential problems associated with copper metallization include difficulties associated with the deposition process for depositing copper and barrier layers onto the substrate. The deposition of a barrier layer using conventional barrier materials and deposition techniques may have difficulty achieving a good nucleation surface to promote  less than 111 greater than  texture in an overlying copper layer for improved electro migration lifetime, and good step coverage in high-aspect-ratio features so that barrier thickness on the sidewall and bottom of trenches and via holes is comparable to barrier thickness in the field. In addition, conventional barrier materials and deposition techniques tend to have increased resistivity, especially as deposition temperatures are lowered to below 380xc2x0 C.
The adhesion and uniform nucleation of CVD Cu on commonly used PVD and CVD barriers is problematic. Organometallic precursors used for CVD Cu tend to prematurely decompose on the barrier surface at the initiation of the deposition, which results in non-uniform nucleation with long nucleation delays as well as poor adhesion. This problem is exacerbated as the CVD Cu thickness is scaled to 100-250 xc3x85. For applications as a seed layer for subsequent electroplating, the CVD Cu thickness cannot exceed 15-20% of the feature size to be electroplated. For example, 0.1 xcexcm structures correspond to 150-200 xc3x85 CVD Cu thin film. For such thin seed films, long and variable nucleation delays (typically 30-60 s) lead to poor process repeatability as well as to discontinuous films within the high aspect ratio features. Adhesion of these films to the underlying barrier is also marginal leading to adhesion failure during electroplating or subsequent CMP process steps used to form the inlaid metal line and via plugs.
Therefore, a need has arisen for a barrier material and method for deposition of the barrier which reduces or suppresses copper diffusion through device layers.
A further need exists for a barrier material and method of deposition that improves adhesion of metallization layers, including adhesion of the barrier to underlying layers and adhesion of copper metallization to the barrier layer.
A further need exists for a barrier material and method of deposition that provides low resistance of the barrier layer to electrical current flow.
A further need exists for a barrier material and method of deposition that provides improved step coverage of microelectronic device features, such as a semiconductor chip interconnect structure, having high-aspect-ratio features.
A further need exists for a barrier material and method of deposition that supports deposition of low resistivity films at relatively low deposition temperatures.
A further need exists for a barrier material and method of deposition that reduces or eliminates copper corrosion.
In accordance with the present invention, a barrier material and method for deposition of the barrier are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed diffusion barriers and methods of deposition. The barrier material comprises a known material such as TaN, TiN, or WNx. Moreover, the barrier may comprise one or more metallic dopants selected from the group consisting of cobalt, ruthenium, platinum, palladium, iridium, rhodium, and tin. As indicated, the dopant can be combined with at least one refractory metal selected from the group consisting of tantalum, tungsten, titanium and chromium, and can also be combined with at least one element selected from the group consisting of carbon, oxygen and nitrogen. A variety of combinations of the dopant or several dopants can be used to address particular difficulties or process integration requirements associated with various device structures. Additionally, a simple binary barrier material such as TaN may also be realized by the present invention. The MOCVD technique for incorporation of the dopant provides a uniform thin film layer with good step coverage and nucleation surface. Co-deposition of the dopant with other materials at varied deposition rates allows manipulation of barrier material characteristics throughout the thickness of the barrier layer, allowing the dopant to have varying concentrations relative to other barrier materials at the barrier interface with overlying and underlying layers by depositing graded composition barrier layers.
In accordance with another aspect of the invention, a semiconductor integrated circuit interconnect structure formed on a substrate is disclosed. The interconnect structure comprises a conductive layer comprised of a metallic material and a barrier layer coupled to the substrate, the barrier layer including an adhesion region comprising a refractory metal, the adhesion region promoting adhesion of the conductive layer to the barrier layer.
In accordance with another aspect of the present invention, a method for forming a microelectronic interconnect structure on a substrate is provided. The method includes depositing a conductive layer and depositing a barrier layer, the barrier layer including an adhesion region coupled to the conductive layer. The adhesion region includes a refractory metal doped with an adhesion promotion material such as cobalt or ruthenium.
A further aspect of the invention provides a microelectronic semiconductor interconnect structure formed on a substrate. The interconnect structure includes a metal layer having copper and a barrier layer comprising a barrier material. The barrier material includes an adhesion region comprised of cobalt, ruthenium, cobalt alloy, of ruthenium alloy material for promoting adhesion between the copper layer and the barrier layer.
The present invention provides a number of important technical advantages. One important technical advantage is the reduced diffusion of copper through the barrier material, due to the thermal budget of the fabrication processes associated with the multi-level interconnect formation and during actual device operation under applied electric fields and possible thermal stress conditions.
Another important technical advantage is thermal stability so that the barrier material remains inert during processing. Another advantage that deposition temperatures can be reduced for compatibility with low-k dielectrics, typically having deposition temperatures of below approximately 375xc2x0 C.
Another important technical advantage is good adhesion of the barrier material to the underlying surface as well as to the copper layer deposited over the barrier, such that the structured integrity of the interconnect structure is preserved through the device fabrication process flow and during device operation.
Another important technical advantage is good nucleation surface to promote  less than 111 greater than  texture in the copper layer deposited on the surface, resulting in improved electro migration reliability lifetime.
Another important technical advantage is low electrical resistivity, such as xcfx81xe2x89xa6500 xcexcxcexa9.cm, and contact/interface resistance to the underlying metal, such as copper, so that low via plug resistance, such as Rxe2x89xa61.5 xcexa9, can be achieved.
Another important technical advantage is good step coverage of the barrier material in high-aspect-ratio interconnect features so that barrier thickness on sidewall and bottom surfaces is comparable to barrier thickness in the field, allowing extendibility in terms of barrier thickness scaling.